The present invention relates generally to digital electronic circuits and, more particularly, to a first-in, first-out memory buffer having the capability of retransmitting previously-read data.
The wide acceptance and current popularity of data transmission is evinced by the proliferation of digital peripheral equipment which is connectable to computer processors or the like. The transmission of data from one piece of equipment to another frequently requires communication between extremely fast operating equipment, such as processors, and relatively slower operating peripheral equipment such as disk storage systems and printers.
The most efficient use of such a system is realized when the several interconnected components of the system can communicate asynchronously, so that the faster operating equipment need not be delayed in order to communicate with the slower peripheral equipment.
It is a well-known practice to employ memory devices as intermediate buffers between the components of the system for storing data written therein by the transmitting equipment at one speed and for reading therefrom by receiving equipment at another speed. With this arrangement, it is imperative that memory storage space is available when the transmitting equipment transmits data. Moreover, when the memory storage space is full, it is necessary that the transmitting equipment be signaled so that further transmission cannot be accomplished. It is equally important that the destination equipment be signaled by the intermediate buffer when the memory storage space is empty so that further reading therefrom cannot be accomplished until additional data has been written therein by the transmitting equipment.
In the past, such requirements have been met by shift registers which serially write digital words therein at a desired speed, and which read serially therefrom at a different speed. Such devices are of limited storage and have unacceptable delay times. More recently, random access memories (RAM's) have been developed which have a first-in first-out (FIFO) characteristic. These memories can be quickly accessed to read out the oldest data stored in the memory. The movement of data within such memory is managed by a control section which maintains an account of which storage cells hold effective data. See, for example, U.S. Pat. Nos. 4,151,068 and 4,459,681.
Such asynchronous FIFO memories are normally equipped with status flag circuitry to detect various degrees of fullness of the memory array including EMPTY, FULL, HALF-FULL and various other fractions of the total memory capacity. However, there is often a need for a status flag to detect degrees of fullness other than these fixed fractions. As such, the users frequently desire the status flags that can be programmed and reprogrammed into the FIFO. See, for example, U.S. Pat. No. 5,084,841, "Programmable Status Flag Generator FIFO Using Gray Code," issued Jan. 28, 1992, and assigned to the same assignee as the present invention.
FIFO's are frequently used in data communications systems which include error detection schemes in the receiving module. In such a system, it is often desired to have a data transmission sequence repeated in the event that a burst or random error along the communications link may have corrupted the transmitted data. For this reason, FIFO's having a retransmit mode are currently available.
In currently available FIFO memory devices having retransmit, the implementation of this function has had several disadvantages. The usual way to offer this feature has been to allow the user to reset the read address pointer to an initial location (Word 0) of the FIFO when a retransmit was desired. This is not useful if the total number of write operations since the reset exceeds the depth of the FIFO. For example, assuming a FIFO having a depth of 1,024 words, a write process may start at Word 0 and write up to Word 1023. If five hundred read operations and four hundred write operations occur during the next time interval, the FIFO will then be one hundred write operations short of being full. At this instant, the write address pointer will be directed at Word 400 and the read address pointer at Word 500. If retransmit is now asserted, the read address pointer will be reset to Word 0, and the FIFO will read Words 0 through 499. The important thing to note here is that the first four hundred words read during this retransmit operation are newer than the last one hundred words. This should not occur since, by definition, the first four hundred words sent during the retransmit operation should be older than the last one hundred words written.
Other problems also occur with previous retransmit methods, such as the condition of the ALMOST FULL, ALMOST EMPTY and HALF FULL status flags which are present on many FIFO's. Status flag logic commonly performs a full subtract to establish status flags, or maintains comparisons of the read and write address pointers to look for specific differences, such as reads being 512 words behind writes. The former method is typically slower for deep FIFO's due to the size of the subtract. Where a retransmit function is provided, the latter method becomes difficult to implement because the compares look only for specific flag differences to establish status of the flags. If, for example, the compares look for an exact difference of 512 and the retransmit occurs, the HALF FULL may not represent the flag status correctly. Another disadvantage of the current retransmit method is the time delay between the assertion of the retransmit and the appearance of the retransmitted data at the data outputs, as well as the timing problems with the asynchronous assertion of retransmit and the write clock.
In view of the above, it is clear that there exists a need to develop a FIFO apparatus which provides improved retransmit capability over what is currently known in the art.